Hafnium-based and two-dimensional ferroelectric tunnel junctions: a mini review

Ferroelectric tunnel junctions (FTJs), which feature an ultrathin ferroelectric barrier sandwiched between two electrodes, have emerged as a promising candidate for next-generation non-volatile memories. This review focuses on two emerging material systems: CMOS-compatible hafnium-based ferroelectrics and two-dimensional (2D) van der Waals ferroelectrics (e.g., α-In₂Se₃, CuInP₂S₆, and h-BN). It summarizes the latest research progress and concludes by outlining the challenges and future research directions. Ferroelectric tunnel junctions (FTJs) are emerging as promising candidates for next-generation nonvolatile memory applications, offering advantages like fast read/write speeds and high storage density. Recent advancements have focused on integrating CMOS-compatible hafnium-based ferroelectrics and two-dimensional (2D) van der Waals materials to overcome scalability and compatibility challenges. Researchers have explored crystallographic orientation control, composite barrier design, and oxygen vacancy engineering to enhance the tunneling electroresistance (TER) effect in hafnium-based FTJs, achieving TER ratios up to 2 × 10⁷. In 2D FTJs, materials like In₂Se₃ and CuInP₂S₆ have demonstrated colossal TER, leveraging atomic-scale thickness and clean interfaces. These developments highlight the potential of FTJs in ultra-high-density storage and neuromorphic computing. Future research should focus on material discovery and interface control to address challenges like phase stability and scalable synthesis, paving the way for high-performance, low-power electronic devices. This summary was initially drafted using artificial intelligence, then revised and fact-checked by the author. This mini review highlights recent advances in ferroelectric tunnel junctions (FTJs) based on two emerging material platforms: CMOS-compatible hafnium-based ferroelectrics and two-dimensional van der Waals ferroelectrics. We discuss strategies for achieving giant tunneling electroresistance (TER), including crystallographic orientation control, composite barrier design, oxygen vacancy engineering, and heterostructure interface engineering. The review summarizes performance benchmarks, identifies critical challenges such as phase stability and scalable synthesis, and outlines future directions toward next-generation non-volatile memory and computing-in-memory architectures.