TSMC says panel packaging won't replace CoWoS anytime soon for the largest future AI processors — wafer-level tech can scale to 58 massive dies in one package

TSMC is investigating panel-level packaging solutions while advancing its CoPoS technology. According to Kevin Zhang, wafer-level packaging remains more developed than panel-level methods. The company believes wafer-level packaging can support up to 58 large chips in a single package. This technology is seen as more suitable for future AI processors. TSMC is focusing on scaling wafer-level solutions for high-performance applications. Panel-level packaging is still in early development stages. The company does not expect panel packaging to replace CoWoS in the near future.

This highlights the current limitations of panel-level packaging and the continued reliance on wafer-level solutions for advanced AI chip production.