ScRRAMBLe: block-sparse deep learning architecture for analog in-memory computing accelerators

Analog compute-in-memory combines compute and storage using crossbar arrays of non-volatile memory, thus promising to reduce the energy demand for artificial intelligence workloads. Yet, significant challenges limit their scaling. Implementing signed weights using positive conductances requires a differential encoding scheme that substantially increases area. Furthermore, large fully-connected networks must be decomposed and distributed over multiple fan-in limited CIM modules, incurring a large inter-core communication traffic. Consequently, the partial sum of intermediate logits needs to be computed, requiring high-precision analog-to-digital converters, which have area and power consumption. We propose ScRRAMBLe, a block-sparse neural network architecture with input-balanced random routing between the cores to address these challenges. By imposing an input balancing constraint, we implement each signed weight using a single positive conductance, avoiding the area penalties of a fully differential encoding. We introduce block-sparsity in the network by defining connectivity between neural subpopulations and weight sharing across feature dimensions, improving the communication overhead of unstructured sparsity by reducing the number of address bits. Replacing fully-connected layers, we show the ScRRAMBLe achieves 98.95% accuracy (MNIST) with 94.5% inter-core traffic reduction. Integrated with ResNet, ScRRAMBLe yields 90.46% (CIFAR-10) and 70.36% (CIFAR-100) accuracy with >97% traffic reduction.